As the semiconductor technology advances further, such as the very-large-scale-integration (VLSI) techniques, more and more functionalities are incorporated in modern VLSI chips. This allows building of system-on-a-chip (SOC) devices. For example, microprocessors may incorporate floating point units, arithmetic-logic units, memory management units, etc. into one SOC device. Previously, these units were separately produced and connected together as part of a system. In a similar manner, more and more memory, for example the embedded memory, are also being integrated within the SOC device. Some with one-time programmable type of embedded memory such as masked ROM, others with generic memory blocks such as SRAM or DRAM perform various functions or merely serve as an on-chip storage unit.
As more functional units, including embedded memory, are integrated into a SOC device, the probability of failures occurring within the embedded memory or in other functional units increase with the increased integration. To counteract the effects of failures, redundancy is built into the embedded memory so that physical defects introduced by the fabrication process of SOC device can be fixed before packaging it for field operation.
A conventional redundancy configuration 100 of the commodity memory product is shown in the FIG. 1. The conventional redundancy configuration 100 typically employees both row and column redundancies. Thus, the conventional redundancy configuration 100 typically includes spare row decoders 110 and spare column decoders 120. The spare row and column decoders 110 and 120 contain a plurality of row fuses 112 and column fuses 122, respectively. The conventional redundancy configuration 100 also includes a plurality of spare rows 114 and a plurality of spare columns 124 connected to the spare row and column decoders 110 and 120, respectively. The spare rows and columns 114 and 124, respectively, are part of memory blocks 130. The spare rows 114 substitute for defective word lines (not shown) and the spare columns 124 substitute for defective bit lines (also not shown). The conventional way to link the redundant rows and columns to the address lines is through the laser blown fuses.
FIG. 2 illustrates a conventional row redundancy configuration 200 to activate a redundant word line. The conventional row redundancy configuration 200 includes two sets of row address bits 210. Each set may include a plurality of row address bits 210. The first set represents true row address values (XN to X0) and the second set corresponds to complementary row address value (˜XN to ˜X0). As shown in FIG. 2, each row address bit circuit 210 consists of a transistor 212 serially connected to a fuse 214.
The operation of the conventional row redundancy configuration 200 is explained as follows. In FIG. 2, it is assumed that a word line with address XN . . . X2X1X0=10 . . . 010 is defective and needs to be replaced with a redundant row (not shown). In this situation, fuses 214 of the row address bits XN and X1 (from the first set) and their complementary bits ˜XN−1, . . . ˜X2, and ˜X0 (from the second set) are blown. As a result, the redundant word line is activated and the defective word line is deselected.
In this type of row redundancy scheme, to support one redundant word line, the number of fuses required is twice the number of bits per row address. For example, if the memory block has a 10 bit row address, 20 fuses are required to support one redundant word line.
FIG. 3 illustrates a conventional column redundancy configuration 300 to activate a redundant column. The column redundancy uses different method than the row redundancy described above, called “shift redundancy”, to substitute the defective bit lines. It is called “shift redundancy” because the method skips a defective column and shifts to an adjacent column. The shift redundancy method uses fewer fuses to support redundancy than the row redundancy described above.
Referring again to FIG. 3, the conventional column redundancy configuration 300 includes a redirect control signal generator 310, which generates redirect control signals Y=YM . . . Y2Y1Y0. The redirect control signal generator 310 includes fuses 312 that are serially connected to each other. As shown, the redirect control signal generator 310 also includes inverters 314, which produce complimentary redirect control signal ˜Y=˜YM . . . ˜Y2˜Y1˜Y0. The column redundancy configuration 300 also includes a plurality of multiplexors 320. Each multiplexor 320 directs a bit of the column address decoded lines to one of two column select lines.
The operation of the conventional column redundancy configuration 300 is explained as follows. In FIG. 3, it is assumed that column C2 is defective. In this instance, the fuse between nodes Y1 and Y2 is blown open. As a result, bits Y1 and Y0 of the redirect control signal Y signal are high since these nodes are tied to high voltage VDD (correspondingly, the bits ˜Y1 and ˜Y0 of the complimentary redirect control signal ˜Y are both low). Also, bits YM . . . Y2 are low since these are tied to ground (˜YM . . . ˜Y2 are high). The redirect control signals Y and the complimentary redirect control signals ˜Y control the plurality of multiplexors 320. In this instance, the Y signals YM . . . Y2Y1Y0=0 . . . 0011 redirect the column address decoded lines BM . . . . B0 to skip column C2. In other words, signals from BM . . . B2 are shifted to columns CM+1 . . . C3. As a result, the signals BM . . . B0 are transmitted through columns CM+1 . . . C3C1C0.
The row and column redundancy schemes represented by FIGS. 1, 2 and 3 are used to correct errors in the conventional memory device as well as in the embedded memory of the SOC device prior to packaging. As mentioned above, the conventional way to link the redundant rows and columns to the address lines is through blowing the fuses by a laser. Once the errors are corrected, the SOC device is packaged for field operation.
However, there is no conventional way to deal with errors that occur in the field other than to replace the SOC device. In other words, the conventional design of SOC devices does not allow for field reparability. As more and more functionalities are built into the SOC device, the cost of the device increases. Thus the replacement strategy can become very expensive.